1. Technical Field
Various embodiments generally relate to a semiconductor apparatus, and more particularly, to a semiconductor apparatus having a plurality of stacked chips and a semiconductor system having the semiconductor apparatus.
2. Related Art
In order to increase the utilization of a given space within a semiconductor apparatus, a 3 dimensional (3D) semiconductor apparatus, in which a plurality of chips are stacked and packaged in single package, has been proposed. The 3D semiconductor apparatus achieves maximum integration within a given space by vertically stacking two or more chips.
A 3D semiconductor apparatus may have a stacked plurality of chips that are the same type of chip. These chips may also be coupled to each other through wires, metal lines, or edge-wiring. The plurality of chips may also be coupled to each other by employing “Through Silicon Via” (TSV). TSV's may be used to electrically couple all of the stacked chips by vertically penetrating the plurality of stacked chips with “Via”. In this way, the plurality of chips may operate as a single semiconductor apparatus. The package size of a semiconductor apparatus may depend on or may be effected by the type of coupling method used to couple the chips (i.e., wires, metal lines, edge-wiring, or TSV).